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Product Datasheet
May 9, 2007
9.9-12.5Gb/s Optical Modulator Driver
OC-192 Metro and Long Haul Applications Surface Mount Package
TGA4953-SL
Key Features and Performance
* * * * * * * Metro MSA Compatible Wide Drive Range (3V to 10V) Single-ended Input / Output Low Power Dissipation (1.1W at Vo = 6V) Very Low Rail Ripple 25ps Edge Rates (20/80) Small Form Factor - 11.4 x 8.9 x 2 mm - 0.450 x 0.350 x 0.080 inches
Description
The TriQuint TGA4953-SL is part of a series of surface mount modulator drivers suitable for a variety of driver applications and is compatible with Metro MSA standards. The TGA4953-SL consists of two high performance wideband amplifiers combined with off chip circuitry assembled in a surface mount package. A single TGA4953-SL placed between the MUX and Optical Modulator provides OEMs with a board level modulator driver surface mount solution. The TGA4953-SL provides Metro and Long Haul designers with system critical features such as: low power dissipation (1.1W at Vo = 6V), very low rail ripple, high voltage drive capability at 5V bias (6 V amplitude adjustable to 3 V), low output jitter (1ps rms typical), and low input drive sensitivity (250mV at Vo = 6V). The TGA4953-SL requires external DC blocks, a low frequency choke, and control circuitry. The TGA4953-SL is available on an evaluation board. RoHS compliant version available.
TriQuint Semiconductor Texas : (972)994-8465
Primary Applications
* * Mach-Zehnder Modulator Driver for Metro and Long Haul IRZ & Duobinary Applications
Measured Performance
TGA4953-SL Evaluation Board (Metro MSA Conditions) 10.7 Gb/s, Vdd = 5 V, Idd = 210 mA, (Pdc = 1.1W) VOUT = 6 VPP, CPC = 50%, VIN = 500 mVPP Scale: 2 V/div, 15 ps/div
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Product Datasheet
May 9, 2007
TGA4953-SL
TABLE I MAXIMUM RATINGS Symbol VD1 VD2T Drain Voltage VG1 VG2 VCTRL1 VCTRL2 ID1 ID2T | IG1 | | IG2 | | ICTRL1 | | ICTRL2 | PIN VIN PD TCH TM TSTG 1/ 2/ 3/ 4/ Gate Voltage Range Control Voltage Range Drain Supply Current (Quiescent) Gate Supply Current Control Supply Current Input Continuous Wave Power 12.5Gb/s PRBS Input Voltage Power Dissipation Operating Channel Temperature Mounting Temperature (10 Seconds) Storage Temperature Parameter Value 8V -3V to 0V -3V to VD 200 mA 350 mA 15 mA 15 mA 23 dBm 4 VPP 4W 150 C 230 C -65 to 150 C
0 0 0
Notes 1/ 2/ 1/ 1/ 1/ 2/ 1/ 1/ 5/ 1/ 2/ 1/ 2/ 1/ 2/ 3/ 4/
These ratings represent the maximum operable values for this device Combinations of supply voltage, supply current, input power, and output power shall not exceed PD at a package base temperature of 80C When operated at this bias condition with a baseplate temperature of 80C, the MTTF is reduced Junction operating temperature will directly affect the device median time to failure (MTTF). For maximum life, it is recommended that junction temperatures be maintained at the lowest possible levels. Assure VCTRL1 never exceeds VD1, and VCTRL2 never exceeds VD2T during bias up and down sequences.
5/
TriQuint Semiconductor Texas : (972)994-8465
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2
Product Datasheet
May 9, 2007
TGA4953-SL
TABLE II THERMAL INFORMATION Parameter RJC Thermal Resistance (Channel to Backside of Package) Test Conditions VD2T = 4.7V ID2T = 150mA PDISS = 0.71W TBASE = 80C TCH (C) 98 RJC (C/W) 26 MTTF (hrs) >1E6
Note: Thermal transfer is conducted through the bottom of the TGA4953-SL package into the motherboard. The motherboard must be designed to assure adequate thermal transfer to the base plate.
TriQuint Semiconductor Texas : (972)994-8465
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3
Product Datasheet
May 9, 2007
TGA4953-SL
TABLE III RF CHARACTERIZATION TABLE (TA = 25C, Nominal) Parameter Small Signal Bandwidth Saturated Power Bandwidth 0.1, 2, 4 GHz 6 GHz 10 GHz 14 GHz 16 GHz 0.1, 2, 4, 6, 10, 14, 16 GHz 0.1, 2, 4, 6, 10, 14, 16 GHz 3 GHz 30 28 26 19 14 10 15 Test Conditions Min Typ Max Units Notes
8
GHz
12
GHz
Small Signal Gain
dB
1/ 2/
Input Return Loss Output Return Loss Noise Figure Small Signal AGC Range Saturated Output Power
dB
1/ 2/
10
15
dB
1/ 2/
2.5
dB
Midband
30
dB
2, 4, 6, 8 & 10 GHz
25
dBm
6/ 7/
TriQuint Semiconductor Texas : (972)994-8465
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4
Product Datasheet
May 9, 2007
TGA4953-SL
TABLE III RF CHARACTERIZATION TABLE (TA = 25C, Nominal) Parameter Test Conditions VD2T = 8.0V VD2T = 6.5V VD2T = 5.5V VD2T = 4.5V VD2T = 4.0V VIN = 500mVPP VIN = 800mVPP VIN = 250mVPP VIN = 500mVPP VIN = 800mVPP 250mVPP 800mVPP | 500-800 mV in
p-p|
Min 10 8.0 7.0 6.0 5.5
Typ
Max
Units
Notes
Eye Amplitude
VPP
3/ 4/
Additive Jitter (RMS) Q-Factor Delta Eye Amplitude Delta Crossing Percentage
0.9 1.0 26.5 28.5 28.5 32 35 35
2.0 2.0
Ps
5/
V/V 0.45 0.10 6
VPP
%
Table III Notes:
1/ Verified at package level RF test 2/ Package RF Test Bias: Vdd = 5V, adjust VG1 to achieve Idd = 65mA then adjust VG2 to achieve Idd = 200mA, VCTRL1 = -0.2V & VCTRL2 = +0.2 V 3/ Verified by design, SMT assembled onto a demonstration board detailed on sheet 6. 4/ VIN = 250mV, Data Rate = 10.7Gb/s, VD1 = VD2T or greater, VCTRL2 and VG2 are adjusted for maximum output 5/ Computed using RSS Method where JRMS_DUT = (JRMS_TOTAL2 - JRMS_SOURCE2) 6/ Verified at die level on-wafer probe 7/ Power Bias Die Probe: VTEE = 8V, adjust VG to achieve Idd = 175mA 5%, VCTRL = +1.5V 8/ Value is the difference with the 500mV input measurement. Result is the absolute value. Note: At the die level, drain bias is applied through the RF output port using a bias tee, voltage is at the DC input to the bias tee
5
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Product Datasheet
May 9, 2007
TGA4953-SL Demonstration Board
DC Block
Mother Board
DC Block
RFin
RFout
TGA4953-SL Driver Package
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice.
TriQuint Semiconductor Texas : (972)994-8465
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6
Product Datasheet
May 9, 2007
TGA4953-SL Demonstration Board Application Circuit
TGA4953-SL
Notes:
1. C3 and C4 extend low frequency performance thru 30 KHz. For applications requiring low frequency performance thru 100 KHz, C3 and C4 may be omitted 2. C5 is a power supply decoupling capacitor and may be omitted 3. C6 and C7 are power supply decoupling capacitors and may be omitted when driven directly with an op-amp. Impedance looking into VCTRL1 and VCTRL2 is 10k real
TriQuint Semiconductor Texas : (972)994-8465
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Product Datasheet
May 9, 2007
TGA4953-SL Demonstration Board Application Circuit
(Continued)
Recommended Components:
DESIGNATOR C1, C2 C3, C4, C5 C6, C7 C8 L1 L2 R1, R2 DESCRIPTION DC Block, Broadband 10uF Capacitor MLC Ceramic 0.01 uFCapacitor MLC Ceramic 10 uF Capacitor Tantalum 220 uH Inductor 330 nH Inductor 274 Resistor MANUFACTURER Presidio AVX AVX AVX Panasonic or Belfuse Panasonic Panasonic PART NUMBER BB0502X7R104M16VNT9820 0805YC106KA 0603YC103KA TAJT106K016 ELLCTV221M S581-4000-14 ELJ-FAR33MF2 ERJ2RKD274
TriQuint Semiconductor Texas : (972)994-8465
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8
Product Datasheet
May 9, 2007
TGA4953-SL
TGA4953-SL Typical Performance Data is measured in a Test Fixture
Idd Vdd Id1 Id2T
TGA4953-SL Driver RF(in) RF(out)
Vctrl1 Vg1
Vctrl2
Vg2
Test Fixture Block Diagram
TriQuint Semiconductor Texas : (972)994-8465
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Product Datasheet
May 9, 2007
TGA4953-SL
Typical Measured Performance on Demonstration Board 10.7Gb/s 2^31-1, Vdd=5V CPC=50%
Vo=6V Vo=5V
Vo=4V
Vo=3V
Input Signal Vin=500mV
TriQuint Semiconductor Texas : (972)994-8465
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Product Datasheet
May 9, 2007
TGA4953-SL
Typical Measured Performance on Demonstration Board IRZ 2^31-1, Vdd=8V Vin=800mVpp
9.953Gbps 10.7Gbps
11.3Gbps
Input Signal 10.7Gbps
TriQuint Semiconductor Texas : (972)994-8465
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11
Product Datasheet
May 9, 2007
TGA4953-SL
Typical Measured Performance on Demonstration Board Duobinary 2^31-1, Vdd=10.5V Vin=800mVpp
10.7Gbps 11.2Gbps
12.5Gbps
Input Signal 10.7Gbps
TriQuint Semiconductor Texas : (972)994-8465
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12
Product Datasheet
May 9, 2007
TGA4953-SL
Typical Bias Conditions Vdd=5V
Vo(V) 6 5 4 3
Vg1(V) -0.66 -0.66 -0.66 -0.66
Vg2(V) -0.57 -0.59 -0.67 -0.74
Idd 221 198 172 147
Vctrl2 +0.22 +0.04 -0.14 -0.34
Notes: 1. Vdd=5V, Id1=65mA, and Vctrl1=-0.2V 2. Vin=500mVpp 3. 50%CPC 4. Actual bias points may be different.
TriQuint Semiconductor Texas : (972)994-8465
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Product Datasheet
May 9, 2007
TGA4953-SL
Demonstration Board - Bias ON/OFF Procedure
Vdd=5V, Vo=6Vamp, CPC=50% (Hot Pluggable)
Bias ON Bias OFF
1. Disable the output of the PPG 1. Disable the output of the PPG 2. Set Vdd=0V Vctrl1=0V Vctrl2=0 Vg1=0V 2. Set Vctrl2=0V and Vg2=0V 3. Set Vdd=0V 3. Set Vg1=-1.5V Vg2=-1.5V Vctrl1=-0.2V 4. Set Vctrl1=0V 4. Increase Vdd to 5V observing Idd. 5. Set Vg2=0V - Assure Idd=0mA 6. Set Vg1=0V 5. Set Vctrl2=+0.2V - Idd should still be 0mA 6. Make Vg1 more positive until Idd=65mA. - This is Id1 (current into the first stage) - Typical value for Vg1 is -0.65V 7. Make Vg2 more positive until Idd=220mA. - This sets Id2T to 155mA. - Typical value for Vg2 is -0.55V 8. Enable the output of the PPG. - Set Vin=500mV 9. Output Swing Adjust: Adjust Vctrl2 slightly positive to increase output swing or adjust Vctrl slightly negative to decrease the output swing. - Typical value for Vctrl2 is +0.22V for Vo=6V. 10. Crossover Adjust: Adjust Vg2 slightly positive to push the crossover down or adjust Vg2 slightly negative to push the crossover up. - Typical value for Vg2 is -0.57V to center crossover with Vo=6V.
TriQuint Semiconductor Texas : (972)994-8465
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Product Datasheet
May 9, 2007
TGA4953-SL
Production - Initial Alignment - Bias Procedure
Vdd=5V, Vo=6Vamp, CPC=50% (Hot Pluggable)
Bias Network Initial Conditions Vg1=-1.5V Vg2=-1.5V Vctrl1=-0.2V Vctrl2=+.1V Vdd=5V
Remove Vg1, Vg2, Vctrl1, Vctrl2, and 1. Disable the output of MUX Vdd in any sequence. 2. Apply Vg1, Vg2, Vctrl1, Vctrl2, and Vdd in any sequence. Note: If Vdd is applied first Idd could reach near 400mA. 3. Make Vg1 more positive until Idd=65mA. - This is Id1 (current into the first stage) - Typical value for Vg1 is -0.65V 4. Make Vg2 more positive until Idd=220mA. - This sets Id2T to 155mA. - Typical value for Vg2 is -0.55V 5. Enable the output of the MUX. - Set Vin=500mV 6. Output Swing Adjust: Adjust Vctrl2 slightly positive to increase output swing or adjust Vctrl2 slightly negative to decrease the output swing. - Typical value for Vctrl2 is +0.22V for Vo=6V. 7. Crossover Adjust: Adjust Vg2 slightly positive to push the crossover down or adjust Vg2 slightly negative to push the crossover up. - Typical value for Vg2 is -0.57V to center crossover with Vo=6V.
Bias ON
Bias OFF
TriQuint Semiconductor Texas : (972)994-8465
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Product Datasheet
May 9, 2007
TGA4953-SL
Production - Post Alignment - Bias Procedure
Vdd=5V, Vo=6Vamp, CPC=50% (Hot Pluggable)
Bias Network Initial Conditions Vg1= As found during initial alignment Vg2=-As found during initial alignment Vctrl1=-0.2V Vctrl2=As found during initial alignment Vdd=5V
Bias ON
1. Mux output can be either Enabled or Disabled 2. Apply Vg1, Vg2, Vctrl1, Vctrl2, and Vdd in any sequence. Note: If Vdd is applied first Idd could reach near 400mA. 3. Enable the output of the MUX 4. Output Swing Adjust: Adjust Vctrl2 slightly positive to increase output swing or adjust Vctrl slightly negative to decrease the output swing. 5. Crossover Adjust: Adjust Vg2 slightly positive to push the crossover down or adjust Vg2 slightly negative to push the crossover up.
Bias OFF
Remove Vg1, Vg2, Vctrl1, Vctrl2, and Vdd in any sequence.
TriQuint Semiconductor Texas : (972)994-8465
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16
Product Datasheet
May 9, 2007
TGA4953-SL
Production - Initial Alignment - IRZ Bias Procedure
Vdd=8V, Vo=6Vamp (Hot Pluggable)
Bias Network Initial Conditions Vg1=-1.5V Vg2=-2.0V Vctrl1=+1.0V Vctrl2=+2.0V Vdd=8V
Remove Vg1, Vg2, Vctrl1, Vctrl2, and 1. Disable the output of MUX Vdd in any sequence. 2. Apply Vg1, Vg2, Vctrl1, Vctrl2, and Vdd in any sequence. Note: If Vdd is applied first Idd could reach near 400mA. 3. Make Vg1 more positive until Idd=80mA. - This is Id1 (current into the first stage) - Typical value for Vg1 is -0.55V 4. Enable the output of the MUX. - Set Vin=800mV 5. Crossover Adjust: Adjust Vg2 slightly negative to push the crossover towards zero level. 6. Output Swing Adjust: Adjust Vctrl2 slightly positive to increase output swing or adjust Vctrl2 slightly negative to decrease the output swing. 7. Duty Cycle Fine Tune: Adjust Vctrl1 slightly negative to reduce duty cycle percentage. 8. Readjust Vctrl2 for proper output amplitude.
Bias ON
Bias OFF
TriQuint Semiconductor Texas : (972)994-8465
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Product Datasheet
May 9, 2007
TGA4953-SL Mechanical Drawing
0.047 0.350 0.255 0.254 0.224 0.175 0.096 0.074 0.024 0.000
9
0.113 0.127 0.178 0.207 0.247 0.304 0.327 0.378 0.407 0.438 0.327 0.254 0.175 0.126
ORIENTATION MARK 19 25 18 26 27 321 LID 0.020 SIDEWALL Vd1 N/C Vctrl1 RF In GND GND GND GND GND GND GND GND GND
10 11 12 13 14 15 16 17 20 21 22 23 24
87654
0.080 REF.
0.000 0.017 0.068 0.087 0.118 0.163 0.167 0.228 0.268 0.318 0.363 0.367 0.402 0.412 0.450
Pin #1 Pin #2 Pin #3 Pin #4 Pin #5 Pin #6 Pin #7 Pin #8 Pin #9 Pin #10 Pin #11 Pin #12 Pin #13 Pin #14 N/C N/C Vg1 N/C N/C Vg2 N/C N/C RF Out N/C N/C Vd2T N/C Vctrl2 0.025 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.027 x 0.018 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 Pin #15 Pin #16 Pin #17 Pin #18 Pin #19 Pin #20 Pin #21 Pin #22 Pin #23 Pin #24 Pin #25 Pin #26 Pin #27 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.020 x 0.018 0.023 x 0.033 0.049 x 0.049 0.023 x 0.033 0.023 x 0.033 0.049 x 0.049 0.023 x 0.033 0.023 x 0.033 0.023 x 0.033
Notes: 1. Dimensions: Inches. Tolerance: Length and Width: +/-.003 inches. Height +/-.006 inches. Adjacent pad to pad spacing: +/- .0002 inches. Pad Size: +/- .001 inches. 2. Surface Mount Interface: Material: RO4003 (thickness=.008 inches), 1/2oz copper (thickness=.0007 inches) Plating Finish: 100-350 microinches nickel underplate, with 5-10 microinches flash gold overplate.
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Product Datasheet
May 9, 2007
TGA4953-SL
Recommended Surface Mount Package Assembly
Proper ESD precautions must be followed while handling packages. Clean the board with acetone. Rinse with alcohol. Allow the circuit to fully dry. TriQuint recommends using a conductive solder paste for attachment. Follow solder paste and reflow oven vendors' recommendations when developing a solder reflow profile. Typical solder reflow profiles are listed in the table below. Hand soldering is not recommended. Solder paste can be applied using a stencil printer or dot placement. The volume of solder paste depends on PCB and component layout and should be well controlled to ensure consistent mechanical and electrical performance. This package has little tendency to self-align during reflow. Clean the assembly with alcohol.
Typical Solder Reflow Profiles
Reflow Profile
Ramp-up Rate Activation Time and Temperature Time above Melting Point Max Peak Temperature Time within 5 C of Peak Temperature Ramp-down Rate
SnPb
3 C/sec 60 - 120 sec @ 140 - 160 C 60 - 150 sec 240 C 10 - 20 sec 4 - 6 C/sec
Pb Free
3 C/sec 60 - 180 sec @ 150 - 200 C 60 - 150 sec 260 C 10 - 20 sec 4 - 6 C/sec
Ordering Information
Part TGA4953-SL,RoHS Package Style Land Grid Array Surface Mount (RoHS Compliant)
GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should be observed during handling, assembly and test.
TriQuint Semiconductor Texas : (972)994-8465 Fax (972)994-8504 Web: www.triquint.com
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